Spur-reduction frequency synthesizer exploiting randomly selected PFD

Te Wen Liao*, Jun Ren Su, Chung-Chih Hung

*Corresponding author for this work

Research output: Contribution to journalArticle

11 Scopus citations

Abstract

This brief presents a low-spur phase-locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator to reduce the reference spur at the output of the PLL. A novel random clock generator is presented to perform the random selection of the phase frequency detector control for the charge pump in locked state. The proposed frequency synthesizer was fabricated in a TSMC 0.18-μm CMOS process. The proposed PLL achieved phase noise of-93 dBc Hz with a 600-kHz offset frequency and reference spurs below-72 dBc.

Original languageEnglish
Article number6176004
Pages (from-to)589-592
Number of pages4
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume21
Issue number3
DOIs
StatePublished - 1 Jan 2013

Keywords

  • Low spur synthesizer
  • phase-locked loop (PLL)
  • voltage-controlled oscillator (VCO)

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