Spice-compatible flash EEPROM model feasible for transient and program/erase cycling endurance simulation

Steve S. Chung*, C. M. Yih, S. S. Wu, H. H. Chen, Gary Hong

*Corresponding author for this work

Research output: Contribution to journalConference article

13 Scopus citations

Abstract

A complete Spice-compatible model for stacked-gate flash E2PROM cells has been successfully developed. It includes an accurate dc I-V model, a gate current model for Channel Hot Electron (CHE) programming, and a channel Fowler-Nordheim (FN) current model for erase. Program and erase induced oxide damage are also included in the model. For the first time, it allows the simulation of the programming/erase transient and the P/E cycling endurance characteristics using the present analytical approach. It provides an easy way for applications to cell design optimization and reliability evaluation for device and circuit designers.

Original languageEnglish
Pages (from-to)179-182
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
StatePublished - 1 Dec 1999
Event1999 IEEE International Devices Meeting (IEDM) - Washington, DC, USA
Duration: 5 Dec 19998 Dec 1999

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