Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learning

Chia Ling Chang*, Charles H.P. Wen, Jayanta Bhadra

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

A learning-and-filtering algorithm is proposed to uncover cross-timeframe state-pair constraints for speeding up SAT solving of bounded sequential equivalence checking (BSEC) problems. First, relaxed Boolean functions for flip-flop states at respective timeframes are learned from a small number of simulation data to derive the initial set of the state-pair candidates. Next, each candidate is examined and removed if both values in such a candidate have coordinately appeared during the simulation. Then, the validity of the remaining candidates is checked against the corresponding augmented circuit. Last, only the true constraints are annotated to the BSEC problems to facilitate SAT solving. All benchmark circuits are synthesized under 10 configurations to produce different BSEC problems. Experimental results show that the new SAT solving runs 2-order faster in average compared to using MiniSAT 2.0 only. Moreover, given a time bound, the total number of timeframes can increase by 8X-20X on 4 larger circuits after applying the proposed framework.

Original languageEnglish
Title of host publicationInternational Test Conference, ITC 2009 - Proceedings
DOIs
StatePublished - 15 Dec 2009
EventInternational Test Conference, ITC 2009 - Austin, TX, United States
Duration: 1 Nov 20096 Nov 2009

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539

Conference

ConferenceInternational Test Conference, ITC 2009
CountryUnited States
CityAustin, TX
Period1/11/096/11/09

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