Spatial and energetic distribution of border traps in the dual-layer HfO2/Si O2 high- k gate stack by low-frequency capacitance-voltage measurement

Wei Hao Wu*, Bing-Yue Tsui, Mao Chieh Chen, Yong Tian Hou, Yin Jin, Hun Jan Tao, Shih Chang Chen, Mong Song Liang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

15 Scopus citations

Abstract

Threshold voltage instability measured by the pulse current-voltage technique has been recognized as the transient charging and discharging of the preexisting bulk traps in Hf-based high- k gate dielectrics, and these high- k traps or called border traps can instantly exchange charge carriers with the underlying Si substrate by tunneling through the thin interfacial oxide. Based on an elastic tunneling model through trapezoidal potential barriers, the spatial and energetic distribution of border traps in the Hf O2 Si O2 high- k gate stack can be profiled as a smoothed, three-dimensional mesh by measuring the low-frequency capacitance-voltage characteristics of high- k metal-oxide-semiconductor capacitors with n -type Si substrate.

Original languageEnglish
Article number162911
JournalApplied Physics Letters
Volume89
Issue number16
DOIs
StatePublished - 25 Oct 2006

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