Source-side engineering to increase holding voltage of LDMOS in a O.5-m 16-V BCD technology to avoid latch-up failure

Wen Yi Chen*, Ming-Dou Ker, Yeh Ning Jou, Yeh Jen Huang, Geeng Lih Lin

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

To avoid latch-up failure in high voltage integrated circuits, a source-side engineering technique for on-chip ESD protection nLDMOS is proposed in this work. Experimental results have been verified in a O.5-μm 16-V bipolar CMOS DMOS technology. Measurement results from transmission-line-pulsing system show that the proposed source-side engineering method can effectively increase the holding voltage of the nLDMOS from 10.5V to 16.2V. Transient-induced latch-up tests show that the proposed source-side engineering technique significantly improves the latch-up immunity of nLDMOS in on-chip ESD protection circuit

Original languageEnglish
Title of host publicationProceedings of the 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009
Pages41-44
Number of pages4
DOIs
StatePublished - 16 Nov 2009
Event2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009 - Suzhou, China
Duration: 6 Jul 200910 Jul 2009

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009
CountryChina
CitySuzhou
Period6/07/0910/07/09

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