Low contact resistance (Rc) is key to boost device performance for sub-10nm node. At VLSI Technology Symposium 2016 Samsung reported they reduced Rc by 10% from 14nm to 10nm bulk FinFET technology . TSMC in their beyond 10nm node FinFET paper reported reducing S/D (source/drain) parasitic resistance and enhanced contact process  and at IEDM-2016 reported 7nm FinFET reduced S/D parasitic resistance and developed a novel contact process . A complete session #7 was dedicated to 'Contact Resistance Innovations for Sub 10nm Scaling' with 4 papers at the VLSI Technology Symposium 2016 [4-7]. To achieve Rc in the low E-9 Ωcm2 requires active dopant carrier concentration >5E20/cm3 to low E21/cm3. For SiP n+ S/D contacts P >1E21/cm3 active dopant carrier concentration is realized with laser melt annealing resulting in Rc <1E-9 Ωcm2 . For 70%-SiGe p+ S/D contacts IMEC reported using pre and post Ge amorphous implants to boost the B-implant activation with nsec laser melt annealing to reduce Rc from 1.2E-8 Ωcm2 to 2.1E-9 Ωcm2 . IBM/GF on the other hand reported reducing SiGe p+ S/D Rc from 1.3E-8 Ωcm2 to 1.9E-9 Ωcm2 by using a thin 12nm 100%-Ge trench-epi and switching from a p+ Ge:B to a p+ Ge:B:group-III metastable alloy for surface interface doping . The group-III Me-alloy in Ge boosted p+ dopant activation from ∼1E19/cm3 with B to ∼8E20/cm3 with Ge+Me-alloy. They mentioned no difference between msec non-melt and nsec melt laser annealing.