SOI (Silicon-on-insulator) for high speed ultra large scale integration

Chen-Ming Hu*

*Corresponding author for this work

Research output: Contribution to journalArticle

13 Scopus citations

Abstract

Bulk complementary metal-oxide-semiconductor (CMOS) technology scaling can not sustain the historical rate of speed increase. A realistic target for silicon-on-insulator (SOI) delay and power reductions in comparison to bulk technology are 40% and 30%, independent of scaling, mostly through capacitance reduction. Denser isolation allows more compact layout and easy integration of different high speed (E/D NMOS), low power (CMOS), analog (bipolar, grounded-body CMOS) and memory devices. Silicon device speed record (13 ps at 1.5 V, 300 K) has been set with SOI E/D NMOS. Leakage current due to steady state and transient floating-body induced threshold lowering (FITL) is a device issue which deserves more attention.

Original languageEnglish
Pages (from-to)365-369
Number of pages5
JournalJapanese Journal of Applied Physics
Volume33
Issue number1
DOIs
StatePublished - 1 Jan 1994

Keywords

  • CMOS
  • Scaling
  • Silicon-on-insulator
  • Sol

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