SOI and device scaling

Chen-Ming Hu*

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

7 Scopus citations


With device and process optimization and an accurate SPICE model for circuit simulation, silicon on insulator (SOI) technology should be able to deliver up to 25% speed improvement over bulk technology. In an environment of rapid bulk technology scaling, such performance improvement may or may not outweigh the concern for known or unknown risks. The prospect for SOI should improve with scaling towards 0.1 μm, when new gate and S/D technologies make fully depleted SOI technology compatible with low Vt and low Vcc applications, especially if the rate of technology evolution slows down for technical or economic reasons.

Original languageEnglish
Number of pages4
StatePublished - 1 Dec 1998
EventProceedings of the 1998 IEEE International SOI Conference - Stuart, FL, USA
Duration: 5 Oct 19988 Oct 1998


ConferenceProceedings of the 1998 IEEE International SOI Conference
CityStuart, FL, USA

Fingerprint Dive into the research topics of 'SOI and device scaling'. Together they form a unique fingerprint.

Cite this