With device and process optimization and an accurate SPICE model for circuit simulation, silicon on insulator (SOI) technology should be able to deliver up to 25% speed improvement over bulk technology. In an environment of rapid bulk technology scaling, such performance improvement may or may not outweigh the concern for known or unknown risks. The prospect for SOI should improve with scaling towards 0.1 μm, when new gate and S/D technologies make fully depleted SOI technology compatible with low Vt and low Vcc applications, especially if the rate of technology evolution slows down for technical or economic reasons.
|Number of pages||4|
|State||Published - 1 Dec 1998|
|Event||Proceedings of the 1998 IEEE International SOI Conference - Stuart, FL, USA|
Duration: 5 Oct 1998 → 8 Oct 1998
|Conference||Proceedings of the 1998 IEEE International SOI Conference|
|City||Stuart, FL, USA|
|Period||5/10/98 → 8/10/98|