Soft error rate reduction using redundancy addition and removal

Kai-Chiang Wu*, Diana Marculescu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

22 Scopus citations

Abstract

Due to current technology scaling trends such as shrinking feature sizes and reducing supply voltages, circuit reliability has become more susceptible to radiation-induced transient faults (soft errors). Soft errors, which have been a great concern in memories, are now a main factor in reliability degradation of logic circuits. In this paper, we propose a novel framework based on redundancy addition and removal (RAR) for soft error rate (SER) reduction. Several metrics and constraints are introduced to guide our proposed framework towards SER reduction in an efficient manner. Experimental results show that up to 70% reduction in output failure probability can be achieved with relatively low area overhead.

Original languageEnglish
Title of host publication2008 Asia and South Pacific Design Automation Conference, ASP-DAC
Pages559-564
Number of pages6
DOIs
StatePublished - 21 Aug 2008
Event2008 Asia and South Pacific Design Automation Conference, ASP-DAC - Seoul, Korea, Republic of
Duration: 21 Mar 200824 Mar 2008

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2008 Asia and South Pacific Design Automation Conference, ASP-DAC
CountryKorea, Republic of
CitySeoul
Period21/03/0824/03/08

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  • Cite this

    Wu, K-C., & Marculescu, D. (2008). Soft error rate reduction using redundancy addition and removal. In 2008 Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 559-564). [4484014] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2008.4484014