The advent of next-generation sequencing has made a great impact on many applications from precision medicine to new drug discovery, leading to an explosion in sequencing of individual genomes. This motivates the research of FPGA acceleration for genome sequencing algorithms to complement the computation capabilities of conventional CPU systems. The recently developed SMEM seeding algorithm, which is based on FMD-index, becomes a time-consuming computation kernel in genome sequencing, but it has not been well studied. The fundamental challenge of accelerating the SMEM algorithm is to handle its large volume of random memory accesses. While the state-of-the-art SMEM accelerator attempts to achieve high memory bandwidth by sacrificing the performance of individual processing elements to maximize the task-level parallelism, this design methodology suffers serious inefficiency of resource utilization and does not scale well for future technology advances. To resolve these impediments, we propose SMEM++, a pipelined and time-multiplexed FPGA accelerator for the SMEM algorithm. SMEM++ features a fully pipelined processing element design that significantly improves the efficiency of FPGA on-chip resource utilization. Moreover, we design a communication interface adapter to make the accelerator compatible to the designated CPU-FPGA platform, increasing its portability. Our experiments on the Intel HARPv2 platform show that SMEM++ outperforms CPU by 24x, and outperforms the state-of-the-art SMEM accelerator design by 6.3x, even with 43% less logic resource consumption.