Next-generation sequencing motivates the researchof FPGA acceleration for genome sequencing algorithms. Therecently developed quadratic-time SMEM seeding algorithmbecomes a time-consuming computation kernel in genomesequencing, but it has not been well studied. The fundamentalchallenge of accelerating the SMEM algorithm is to handle itslarge volume of random memory accesses. While the state-ofthe-art SMEM accelerator attempts sacrifices the performanceof individual processing elements to maximize the task-levelparallelism, this methodology suffers a serious resource underutilizationissue. Therefore, we propose SMEM++, a pipelinedand time-multiplexed FPGA accelerator for SMEM algorithm.SMEM++ adopts the canonical non-blocking pipelinemethodology and implements a fully pipelined acceleratorwith initiation interval equal to one. Moreover, we designa communication interface adapter to make the acceleratorcompatible to the target platform interface and increase itsportability. Experiments on the Intel HARPv2 platform showthat SMEM++ outperforms the original software by 24x, andoutperforms the state-of-the-art SMEM accelerator design by6.3x, with 43% less logic resource usage.