Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection

Ghosh Amlan, Rao Rahul M., Jae-Joon Kim, Ching-Te Chuang, Brown Richard B.

Research output: Contribution to journalArticle

8 Scopus citations

Abstract

The need for efficient and accurate detection schemes to assess the impact of process variations on the parametric yield of integrated circuits has increased in the nanometer design era. In this paper, the difference of rise and fall slew is presented as another process-variation metric along with the delay in determining the relative mismatch between the drive strengths of nMOS and pMOS devices. The importance of considering both of these metrics is illustrated, and a new slew-rate monitoring circuit is presented for measuring the difference of rise and fall slew of a signal on the critical path of a circuit. Sensitivity analysis with multiple pulses as input has also been investigated. Bias generator circuits that track nMOS and pMOS threshold voltages have been incorporated, which makes the design less susceptible to process variation. Design considerations, simulation results, and characteristics of the slew-rate monitor circuitry in a 65-nm IBM CMOS process are presented, and a sensitivity of 50 MHz/50 ps for single pulse input is achieved. The measurement sensitivity of a fabricated slew-rate monitor in a 65-nm IBM CMOS technology is 0.11 V/mu s, with 1089 pF as the output load of the slew-rate monitor.
Original languageEnglish
Pages (from-to)1683-1692
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume21
Issue number9
DOIs
StatePublished - Sep 2013

Keywords

  • Process variation compensation; process variation detection; slew; slew-rate monitor
  • NOISE MARGIN CRITERIA; LOGIC-CIRCUITS; DELAY; DESIGN

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