Skillfully diminishing antenna effect in layer assignment stage

Chih Chien Lin, Wen Hao Liu, Yih-Lang Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Antenna effect is an important issue that critically impacts the reliability and yield of integrated circuits. The dynamic-programming-based (DP-based) layer assignment method has been adopted to minimize antenna violation by enumerating all possible solutions and pruning inferior solutions. However, the complexities of modern circuits have significantly increased, likely causing the DP-based method to consume much more runtime and memory space. In this paper, we propose a skillful method to effectively Diminish Antenna effect in Layer Assignment Stage (DALAS). Unlike previous work that needs to search for separator locations and thus requires exploring much more solution space, DALAS does not need to search for separator locations and can deal with local and global antenna effects while trying to keep total via count and total overflow minimal. Experiment results show that DALAS is the first work to expel all antenna violations with similar via count to that produced by previous works [3][5] for the benchmarks in ISPD'08 Global Routing Contest.

Original languageEnglish
Title of host publicationTechnical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
PublisherIEEE Computer Society
ISBN (Print)9781479927760
DOIs
StatePublished - 1 Jan 2014
Event2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 - Hsinchu, Taiwan
Duration: 28 Apr 201430 Apr 2014

Publication series

NameTechnical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

Conference

Conference2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
CountryTaiwan
CityHsinchu
Period28/04/1430/04/14

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