Skew-aware functional timing analysis against setup violation for post-layout validation

Pin Ru Jhao, Denny C.Y. Wu, Charles H.P. Wen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Beyond the deep sub-micron era, clock skew is becoming an indispensable factor in post-layout timing and contributes significant delay during signal propagation in paths. Although Functional Timing Analysis (FTA) can provide accurate timing by identifying functionally false paths, clock skew is not yet considered. Therefore, we are motivated to propose a skew-aware functional-timing-analysis engine (named Sk-FTA) for better post-layout validation of designs. In particular, Sk-FTA can save more cost in checking setup-time violations and filters false alarms. Our experimental results show that given three different clock networks, Sk-FTA induces more accurate delay from removing functionally false paths (e.g. 60% less for s13207 under clock tree 3) when comparing with the skew-aware static timing analysis (Sk-STA). Moreover, Sk-FTA eminently yields fewer setup-time violations than Sk-STA does on benchmark circuits. In particular, for vga lcd, all 512 setup-time violations reported by Sk-STA are proved redundant and thus removed, manifesting the power of Sk-FTA.

Original languageEnglish
Title of host publicationProceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages67-72
Number of pages6
ISBN (Print)9781538651803
DOIs
StatePublished - 11 Sep 2018
Event2nd IEEE International Test Conference in Asia, ITC-Asia 2018 - Harbin, China
Duration: 15 Aug 201817 Aug 2018

Publication series

NameProceedings - 2nd IEEE International Test Conference in Asia, ITC-Asia 2018

Conference

Conference2nd IEEE International Test Conference in Asia, ITC-Asia 2018
CountryChina
CityHarbin
Period15/08/1817/08/18

Keywords

  • Functional Timing Analysis
  • Skew Aware
  • Timing Validation

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