Beyond the deep sub-micron era, clock skew is becoming an indispensable factor in post-layout timing and contributes significant delay during signal propagation in paths. Although Functional Timing Analysis (FTA) can provide accurate timing by identifying functionally false paths, clock skew is not yet considered. Therefore, we are motivated to propose a skew-aware functional-timing-analysis engine (named Sk-FTA) for better post-layout validation of designs. In particular, Sk-FTA can save more cost in checking setup-time violations and filters false alarms. Our experimental results show that given three different clock networks, Sk-FTA induces more accurate delay from removing functionally false paths (e.g. 60% less for s13207 under clock tree 3) when comparing with the skew-aware static timing analysis (Sk-STA). Moreover, Sk-FTA eminently yields fewer setup-time violations than Sk-STA does on benchmark circuits. In particular, for vga lcd, all 512 setup-time violations reported by Sk-STA are proved redundant and thus removed, manifesting the power of Sk-FTA.