The performance of single-issue RISC cores can be improved significantly with multi-issue architectures (i.e. superscalar or VLIW) by activating the parallel functional units concurrently. However, they suffer high complexity or huge code sizes. In this paper, we borrow some ideas from old vector machines and propose a novel DSP architecture with very compact codes. In our simulations, the DSP has comparable performance to a 5-issue VLIW core with identical computing resources. However, its code sizes are greatly-reduced. The DSP core has been implemented in the TSMC 0.13um CMOS technology, where the operating frequency is 305MHz and the core size is 1.45×1.4 mm2 including 12KB on-chip memory.