Single-issue 1500MIPS embedded DSP with ultra compact codes

Li Chun Lin*, Shih Hao Ou, Tay Jyi Lin, Siang Den Deng, Chih-Wei Liu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The performance of single-issue RISC cores can be improved significantly with multi-issue architectures (i.e. superscalar or VLIW) by activating the parallel functional units concurrently. However, they suffer high complexity or huge code sizes. In this paper, we borrow some ideas from old vector machines and propose a novel DSP architecture with very compact codes. In our simulations, the DSP has comparable performance to a 5-issue VLIW core with identical computing resources. However, its code sizes are greatly-reduced. The DSP core has been implemented in the TSMC 0.13um CMOS technology, where the operating frequency is 305MHz and the core size is 1.45×1.4 mm2 including 12KB on-chip memory.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Pages110-111
Number of pages2
DOIs
StatePublished - 1 Dec 2007
EventASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama, Japan
Duration: 23 Jan 200727 Jan 2007

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

ConferenceASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
CountryJapan
CityYokohama
Period23/01/0727/01/07

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