Single-gate 0.15 and 0.12 μm CMOS with Co salicide technology

Takashi Yoshitomi*, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Hisayo Sasaki Momose, Eiji Morifuji, Toyota Morimoto, Yasuhiro Katsumata, Hiroshi Iwai

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


A high-speed 0.15 μm single-gate Co salicide CMOS technology has been demonstrated, which suppresses short channel effects in 0.15 μm buried channel pMOSFETs by optimizing the fabrication conditions of their extension region. An unloaded CMOS inverter ring-oscillator delay of 19.8 ps has been obtained. At 0.12 μm gate length, 11.4 ps gate delay was observed.

Original languageEnglish
Pages (from-to)543-546
Number of pages4
JournalSolid-State Electronics
Issue number3
StatePublished - 1999

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