Single-ended subthreshold SRAM with asymmetrical write/read-assist

Ming Hsien Tu*, Jihi Yu Lin, Ming Chien Tsai, Shyh-Jye Jou, Ching Te Chuang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

79 Scopus citations


In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive feedback sensing keeper schemes are proposed to improve the read static noise margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T SRAM cell. A 4 Kbit SRAM test chip is implemented in 90 nm CMOS technology. The test chip measurement results show that at 0.2 V V DD , an operation frequency of 6.0 MHz can be achieved with power consumption of 10.4 μW.

Original languageEnglish
Article number5634142
Pages (from-to)3039-3047
Number of pages9
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number12
StatePublished - 15 Nov 2010


  • Low power
  • low voltage
  • single-ended SRAM

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