Simultaneous Switching Noise analysis and low bouncing buffer design

Shyh-Jye Jou*, Wei Chung Cheng, Yu Tao Lin

*Corresponding author for this work

Research output: Contribution to journalConference article

10 Scopus citations

Abstract

An accurate equation to estimate Simultaneous Switching Noise (SSN) in CMOS integrated circuits including the carriers velocity saturation effects of the short-channel MOSFET transistor is proposed. Simulation results show that the proposed close-form equation estimates the SSN precisely and the error is below 5% as compared with HSPICE simulation results. Design procedures of low bouncing tapered buffer that take SSN into consideration are also proposed. Finally, several output buffer design examples are implemented to verify the low bouncing buffer design.

Original languageEnglish
Pages (from-to)545-548
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
DOIs
StatePublished - 1 Jan 1998
EventProceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA
Duration: 11 May 199814 May 1998

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