Simultaneous switching noise analysis and low-bounce buffer design

Shyh-Jye Jou*, W. C. Cheng, Y. T. Lin

*Corresponding author for this work

Research output: Contribution to journalArticle

8 Scopus citations

Abstract

An accurate equation to estimate simultaneous switching noise (SSN) created by CMOS output buffers is proposed. This analytic equation includes the carrier velocity saturation effects of a short-channel MOS transistor. Simulation results show that the proposed closed-form equation estimates the SSN precisely and the error is below 10% as compared with HSPICE simulation results. Design procedures of a low-bounce tapered buffer which take SSN into consideration are also proposed. Several output buffer design examples are demonstrated to show the significant improvement of the low-bounce buffer design. A test chip of the output buffer is implemented to operate at 400 MHz and the measurement results match the design specifications.

Original languageEnglish
Pages (from-to)303-311
Number of pages9
JournalIEE Proceedings: Circuits, Devices and Systems
Volume148
Issue number6
DOIs
StatePublished - 1 Dec 2001

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