Simulation of P- and N-MOSFET hot-carrier degradation in CMOS circuits

P. M. Lee, T. Garfinkel, P. K. Ko, Chen-Ming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

A PMOSFET hot-carrier degradation model has been incorporated into the reliability simulator BERT-CAS, enabling prediction of dynamic circuit-level degradation in which both PMOSFET and NMOSFET degradation play a major role. Comparisons are presented which reveal the good fit obtained between measurement and simulation results.

Original languageEnglish
Title of host publication1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers, VTSA 1991
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages191-195
Number of pages5
ISBN (Electronic)078030036X, 9780780300361
DOIs
StatePublished - 1 Jan 1991
Event1991 International Symposium on VLSI Technology, Systems, and Applications, VTSA 1991 - Taipei, Taiwan
Duration: 22 May 199124 May 1991

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
ISSN (Print)1930-8868

Conference

Conference1991 International Symposium on VLSI Technology, Systems, and Applications, VTSA 1991
CountryTaiwan
CityTaipei
Period22/05/9124/05/91

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    Lee, P. M., Garfinkel, T., Ko, P. K., & Hu, C-M. (1991). Simulation of P- and N-MOSFET hot-carrier degradation in CMOS circuits. In 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers, VTSA 1991 (pp. 191-195). [246684] (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VTSA.1991.246684