Simulation of nanoscale round-top-gate bulk FinFETs with optimal geometry aspect ratio

Yiming Li*, Wei Hsin Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

In this paper, we explore electrical characteristics of a 25 nm round-top-gate FinFET on both bulk silicon and SOI substrates. Assuming an ideal fin angle θ = 90°, device performance of the FinFET with doped and undoped channels are simulated with a three-dimensional quantum correction transport model. Theoretical comparison shows that undoped bulk FinFETs possess promising electrical characteristics among different structures. Effect of non-ideal fin angle and fin height on device performance is investigated in terms of different shortchannel effects. Optimal configuration of structure for the 25 nm round-top-gate bulk FinFETs is drawn to show the strategy of fabrication in nanoscale CMOS devices.

Original languageEnglish
Title of host publication2006 6th IEEE Conference on Nanotechnology, IEEE-NANO 2006
Pages569-572
Number of pages4
StatePublished - 2006
Event2006 6th IEEE Conference on Nanotechnology, IEEE-NANO 2006 - Cincinnati, OH, United States
Duration: 17 Jun 200620 Jun 2006

Publication series

Name2006 6th IEEE Conference on Nanotechnology, IEEE-NANO 2006
Volume2

Conference

Conference2006 6th IEEE Conference on Nanotechnology, IEEE-NANO 2006
CountryUnited States
CityCincinnati, OH
Period17/06/0620/06/06

Keywords

  • Bulk silicon
  • CMOS
  • Fin angle
  • Fin heigth
  • FinFETs
  • Manufacturabilityt
  • Metal gate
  • Modeling and simulation
  • Nanodevice
  • Round-top
  • Short channel effec
  • SOI

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