@inproceedings{1b06907119d54a7eab34772047b47b97,
title = "Simulation of grain-boundary traps effect for 3D vertical gate NAND flash memory cell: from structure geometry to trap description",
abstract = "3D NAND Flash is the most promising memory architecture which can increase capacity continuously without aggressive scaling-down. The performance variability of the memory cell induced by the grain boundaries (GBs) of the poly-Si channel is a major concern. In this work, a full 3D simulation is performed to study the threshold voltage variability. The impact of the 3D structure geometry on the variation induced by the GB traps is discussed. In addition, a discrete-trap approach is also proposed to reflect the true behavior of the GB traps. A smaller variation in the discrete-trap approach is observed due to the local trap effect.",
author = "Wang, {Pei Yu} and Bing-Yue Tsui",
year = "2015",
month = dec,
day = "4",
doi = "10.1109/SNW.2014.7348607",
language = "English",
series = "2014 Silicon Nanoelectronics Workshop, SNW 2014",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2014 Silicon Nanoelectronics Workshop, SNW 2014",
address = "United States",
note = "null ; Conference date: 08-06-2014 Through 09-06-2014",
}