Abstract
3D NAND Flash is the most promising memory architecture which can increase capacity continuously without aggressive scaling-down. The performance variability of the memory cell induced by the grain boundaries (GBs) of the poly-Si channel is a major concern. In this work, a full 3D simulation is performed to study the threshold voltage variability. The impact of the 3D structure geometry on the variation induced by the GB traps is discussed. In addition, a discrete-trap approach is also proposed to reflect the true behavior of the GB traps. A smaller variation in the discrete-trap approach is observed due to the local trap effect.
| Original language | English |
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| Title of host publication | 2014 Silicon Nanoelectronics Workshop, SNW 2014 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781479956777 |
| DOIs | |
| State | Published - 4 Dec 2015 |
| Event | Silicon Nanoelectronics Workshop, SNW 2014 - Honolulu, United States Duration: 8 Jun 2014 → 9 Jun 2014 |
Publication series
| Name | 2014 Silicon Nanoelectronics Workshop, SNW 2014 |
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Conference
| Conference | Silicon Nanoelectronics Workshop, SNW 2014 |
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| Country | United States |
| City | Honolulu |
| Period | 8/06/14 → 9/06/14 |
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Cite this
Wang, P. Y., & Tsui, B-Y. (2015). Simulation of grain-boundary traps effect for 3D vertical gate NAND flash memory cell: from structure geometry to trap description. In 2014 Silicon Nanoelectronics Workshop, SNW 2014 [7348607] (2014 Silicon Nanoelectronics Workshop, SNW 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SNW.2014.7348607