Simulation of grain-boundary induced Vth variability in stackable NAND flash using a Voronoi approach

Ching Wei Yang; Shao Heng Chao; Pin Su

doi:10.1109/NVMTS.2013.6632851

Simulation of grain-boundary induced V_th variability in stackable NAND flash using a Voronoi approach

Ching Wei Yang, Shao Heng Chao, Pin Su

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this work, we employ a novel Voronoi approach to simulate the impact of trap states in the poly-Si channel. Using this method, we investigate the grain boundary induced threshold voltage variability in stackable NAND flash memories. Our study indicates that considering the randomized shape and location of grain boundaries is crucial to the modeling and simulation of these devices.

Original language	English
Title of host publication	2012 12th Annual Non-Volatile Memory Technology Symposium Proceedings, NVMTS 2012
Pages	12-15
Number of pages	4
DOIs	https://doi.org/10.1109/NVMTS.2013.6632851
State	Published - 1 Dec 2012
Event	2012 12th Annual Non-Volatile Memory Technology Symposium, NVMTS 2012 - Singapore, Singapore Duration: 31 Oct 2012 → 2 Nov 2012

Publication series

Name	2012 12th Annual Non-Volatile Memory Technology Symposium Proceedings, NVMTS 2012

Conference

Conference	2012 12th Annual Non-Volatile Memory Technology Symposium, NVMTS 2012
Country	Singapore
City	Singapore
Period	31/10/12 → 2/11/12

Keywords

BE-SONOS
Grain boundary
Voronoi
polycrystalline silicon
stackable NAND flash
variability

Access to Document

10.1109/NVMTS.2013.6632851

Link to publication in Scopus

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Yang, C. W., Chao, S. H., & Su, P. (2012). Simulation of grain-boundary induced V_th variability in stackable NAND flash using a Voronoi approach. In 2012 12th Annual Non-Volatile Memory Technology Symposium Proceedings, NVMTS 2012 (pp. 12-15). [6632851] (2012 12th Annual Non-Volatile Memory Technology Symposium Proceedings, NVMTS 2012). https://doi.org/10.1109/NVMTS.2013.6632851

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abstract = "In this work, we employ a novel Voronoi approach to simulate the impact of trap states in the poly-Si channel. Using this method, we investigate the grain boundary induced threshold voltage variability in stackable NAND flash memories. Our study indicates that considering the randomized shape and location of grain boundaries is crucial to the modeling and simulation of these devices.",

keywords = "BE-SONOS, Grain boundary, Voronoi, polycrystalline silicon, stackable NAND flash, variability",

author = "Yang, {Ching Wei} and Chao, {Shao Heng} and Pin Su",

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Yang, CW, Chao, SH & Su, P 2012, Simulation of grain-boundary induced V_th variability in stackable NAND flash using a Voronoi approach. in 2012 12th Annual Non-Volatile Memory Technology Symposium Proceedings, NVMTS 2012., 6632851, 2012 12th Annual Non-Volatile Memory Technology Symposium Proceedings, NVMTS 2012, pp. 12-15, 2012 12th Annual Non-Volatile Memory Technology Symposium, NVMTS 2012, Singapore, Singapore, 31/10/12. https://doi.org/10.1109/NVMTS.2013.6632851

Simulation of grain-boundary induced V_th variability in stackable NAND flash using a Voronoi approach. / Yang, Ching Wei; Chao, Shao Heng; Su, Pin.

2012 12th Annual Non-Volatile Memory Technology Symposium Proceedings, NVMTS 2012. 2012. p. 12-15 6632851 (2012 12th Annual Non-Volatile Memory Technology Symposium Proceedings, NVMTS 2012).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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