Simulation of grain-boundary induced Vth variability in stackable NAND flash using a Voronoi approach

Ching Wei Yang, Shao Heng Chao, Pin Su

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this work, we employ a novel Voronoi approach to simulate the impact of trap states in the poly-Si channel. Using this method, we investigate the grain boundary induced threshold voltage variability in stackable NAND flash memories. Our study indicates that considering the randomized shape and location of grain boundaries is crucial to the modeling and simulation of these devices.

Original languageEnglish
Title of host publication2012 12th Annual Non-Volatile Memory Technology Symposium Proceedings, NVMTS 2012
Pages12-15
Number of pages4
DOIs
StatePublished - 1 Dec 2012
Event2012 12th Annual Non-Volatile Memory Technology Symposium, NVMTS 2012 - Singapore, Singapore
Duration: 31 Oct 20122 Nov 2012

Publication series

Name2012 12th Annual Non-Volatile Memory Technology Symposium Proceedings, NVMTS 2012

Conference

Conference2012 12th Annual Non-Volatile Memory Technology Symposium, NVMTS 2012
CountrySingapore
CitySingapore
Period31/10/122/11/12

Keywords

  • BE-SONOS
  • Grain boundary
  • Voronoi
  • polycrystalline silicon
  • stackable NAND flash
  • variability

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