Simulation of CMOS circuit degradation due to hot-carrier effects

Khandker N. Quader*, Ping K. Ko, Chen-Ming Hu, Peng Fang, John T. Yue

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Scopus citations

Abstract

By comparing long-term ring-oscillator hot-carrier degradation data and simulation results the authors show that a public-domain circuit simulator, BERT (Berkeley Reliability Tools), can predict CMOS digital circuit speed degradation from transistor DC stress data. Large initial PMOSFET drain current enhancement can result in initial frequency enhancement followed by an initial fast degradation due to the zero crossing effect. The relationship between circuit lifetime and transistor DC stress is examined.

Original languageEnglish
Title of host publicationAnnual Proceedings - Reliability Physics (Symposium)
PublisherPubl by IEEE
Pages16-23
Number of pages8
ISBN (Print)078030473X
DOIs
StatePublished - 1 Mar 1992
EventProceedings of the 30th Annual International Reliability Physics Symposium - San Diego, CA, USA
Duration: 31 Mar 19922 Apr 1992

Publication series

NameAnnual Proceedings - Reliability Physics (Symposium)
ISSN (Print)0099-9512

Conference

ConferenceProceedings of the 30th Annual International Reliability Physics Symposium
CitySan Diego, CA, USA
Period31/03/922/04/92

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  • Cite this

    Quader, K. N., Ko, P. K., Hu, C-M., Fang, P., & Yue, J. T. (1992). Simulation of CMOS circuit degradation due to hot-carrier effects. In Annual Proceedings - Reliability Physics (Symposium) (pp. 16-23). (Annual Proceedings - Reliability Physics (Symposium)). Publ by IEEE. https://doi.org/10.1109/RELPHY.1992.187616