Software-based self-test (SBST) was previously proposed as an on-chip functional test methodology. Achieving a desired full-chip functional fault coverage has always been a challenge because random test program generation (RTPG) alone may not be sufficient. This work investigates the potential of using target test program generation (TTPG) to supplement the RTPG method. The proposed TTPG method utilizes simulation results to develop learned models for the surrounding modules of the block under test. Then, the learned models replace the surrounding modules around the block in the actual test generation process. Because the learned models are much simpler to handle, this method minimizes the cost of functional TPG. For developing the simulation-based learning scheme, we divide the surrounding modules into two categories: Boolean and Arithmetic. We apply different techniques for each category and explain their applicability and limitations. The feasibility and effectiveness of the proposed simulation-based TTPG method in the context of supplementing RTPG for achieving high fault coverage in SBST of a RISC pipelined microprocessor design is demonstrated as well.