Simulation and investigation of random grain-boundary-induced variabilities for stackable NAND flash using 3-D voronoi grain patterns

Ching Wei Yang, Pin Su

Research output: Contribution to journalArticlepeer-review

18 Scopus citations

Abstract

This brief investigates the random grain-boundary (GB)-induced variability in poly-crystalline silicon thin-film transistor for stackable NAND flash applications using 3-D Voronoi grain patterns. Compared with the 1-D and 2-D methods, the 3-D Voronoi grain can show a more realistic threshold-voltage variability when devices are downscaled along the channel height (H ch) direction. Therefore, a full 3-D consideration is needed when modeling the random GB-induced variation.

Original languageEnglish
Article number6766781
Pages (from-to)1211-1214
Number of pages4
JournalIEEE Transactions on Electron Devices
Volume61
Issue number4
DOIs
StatePublished - 1 Jan 2014

Keywords

  • 3-D NAND
  • grain boundary (GB)
  • variability
  • Voronoi

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