Simulating process-induced gate oxide damage in circuits

Robert Tu*, Joseph C. King, Hyungcheol Shin, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

Advanced processing techniques such as plasma etching and ion implantation can damage the gate oxides of MOS devices and thus pose a problem to circuit reliability. In this paper, we present a simulator which predicts oxide failure rates during and after processing and pinpoints strong charging current locations in the layout where changes can be made to improve circuit hot-carrier reliability. We present the models and experimental results used to develop the simulator and demonstrate the usefulness of this simulator.

Original languageEnglish
Pages (from-to)1393-1400
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume44
Issue number9
DOIs
StatePublished - 1 Dec 1997

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