Simulating hot-carrier effects on circuit performance

Chen-Ming Hu*

*Corresponding author for this work

Research output: Contribution to journalArticle

15 Scopus citations

Abstract

Hot carriers cause charge trapping in the gate oxide of MOSFETs and generate interface traps at Si/SiO2 interfaces of MOSFETs and bipolar transistors. Models for N-channel and P-channel MOSFETs and for bipolar transistor degradations have been developed and implemented in an IC reliability simulator BERT. Several comparisons between simulation results and measurements are shown. There remain to be answered questions concerning the presence of excess degradation when the stressing signal frequency is high.

Original languageEnglish
Article number146
JournalSemiconductor Science and Technology
Volume7
Issue number3 B
DOIs
StatePublished - 1 Dec 1992

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