Simple error detection methods for hardware implementation of advanced encryption standard

Chih Hsu Yen*, Bing-Fei Wu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

97 Scopus citations


In order to prevent the Advanced Encryption Standard (AES) from suffering from differential fault attacks, the technique of error detection can be adopted to detect the errors during encryption or decryption and then to provide the information for taking further action, such as interrupting the AES process or redoing the process. Because errors occur within a function, it is not easy to predict the output. Therefore, general error control codes are not suited for AES operations. In this work, several error-detection schemes have been proposed. These schemes are based on the (n+1,n) cyclic redundancy check (CRC) over GF(28), where n ε {4,8,16}. Because of the good algebraic properties of AES, specifically the MixColumns operation, these error detection schemes are suitable for AES and efficient for the hardware implementation; they may be designed using round-level, operation-level, or algorithm-level detection. The proposed schemes have high fault coverage. In addition, the schemes proposed are scalable and symmetrical. The scalability makes these schemes suitable for an AES circuit implemented in 8-bit, 32-bit, or 128-bit architecture. Symmetry also benefits the implementation of the proposed schemes to achieve that the encryption process and the decryption process can share the same error detection hardware. These schemes are also suitable for encryption-only or decryption-only cases. Error detection for the key schedule in AES is also proposed and is based on the derived results in the data procedure of AES.

Original languageEnglish
Pages (from-to)720-731
Number of pages12
JournalIEEE Transactions on Computers
Issue number6
StatePublished - 1 Jun 2006


  • Advanced encryption standard
  • CRC
  • Differential fault attacks
  • Error control code

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