Silicon MOSFET scaling beyond 0.1 micron

Hiroshi Iwai*

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

2 Scopus citations

Abstract

This paper gives an overview of CMOS scaling in the range of sub-0.1 μm. Recent advance in the downsizing of MOSFETs by using various new techniques is described. Possible limitation and of MOSFET downswing is predicted. A future concept of silicon LSIs in 2010's is discussed.

Original languageEnglish
Pages11-18
Number of pages8
StatePublished - 1997
EventProceedings of the 1997 21st International Conference on Microelectronics, MIEL'97. Part 1 (of 2) - Nis, Yugosl
Duration: 14 Sep 199717 Sep 1997

Conference

ConferenceProceedings of the 1997 21st International Conference on Microelectronics, MIEL'97. Part 1 (of 2)
CityNis, Yugosl
Period14/09/9717/09/97

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