Silicon layer stacking enabled by wafer bonding

Chuan Seng Tan*, Kuan-Neng Chen, Andy Fan, Anantha Chandrakasan, Rafael Reif

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

12 Scopus citations

Abstract

Three-dimensional integrated circuits (3-D ICs), in the form of a vertical stack of several interconnected device layers, have many performance, form factor, and integration advantages. The main objective of this work is to develop reliable process technology to enable the fabrication of a vertically interconnected silicon multi-layer stack. Low temperature wafer bonding processes, both copper thermo-compression bonding and silicon dioxide fusion bonding, are studied extensively as key enabling technology. Cu thermocompression bonding is studied for its feasibility as a permanent bond between active layers in a multi-layer stack. Silicon dioxide wafer bonding, on the other hand, is used as a temporary bond to attach a donor wafer to a handle wafer during donor wafer thinning and subsequent layer transfer. Sufficiently high bond strength is obtained with careful surface preparation and activation prior to bonding. Silicon layer can be stacked either in a "face down" or "face up" orientation. Using a combination of wafer bonding and thinning, double-layer stacks in both orientations are fabricated. By repeating these steps on two "face down" double-layer stacks, a four-layer stack is successful demonstrated.

Original languageEnglish
Title of host publicationEnabling Technologies for 3-D Integration
Pages193-204
Number of pages12
DOIs
StatePublished - 29 Jun 2007
Event2006 MRS Fall Meeting - Boston, MA, United States
Duration: 27 Nov 20061 Dec 2006

Publication series

NameMaterials Research Society Symposium Proceedings
Volume970
ISSN (Print)0272-9172

Conference

Conference2006 MRS Fall Meeting
CountryUnited States
CityBoston, MA
Period27/11/061/12/06

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