Silicon integrated high performance inductors in a 0.18μm CMOS technology for MMIC

H. M. Hsu*, J. G. Su, S. C. Wong, Y. C. Sun, C. Y. Chang, T. Y. Huang, C. C. Tsai, C. H. Lin, R. S. Liou, R. Y. Chang, T. H. Yeh, C. H. Chen, C. F. Huang, H. D. Huang, C. W. Chen

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

15 Scopus citations

Abstract

This paper presents a complete portfolio of silicon integrated inductors in a 0.18μm CMOS technology. In addition to inductor design, we also present a complete optimization methodology with associated modeling and key characterization. Our inductor quality factors have been enhanced by optimizing patterned ground shield and taper coils, or use Copper metallization. Quality-factor peak can further be optimized at application-specific frequency band with our optimization algorithm. To facilitate IC design with inductors, a novel model considering eddy current loss was developed. Finally, to integrate inductors into a system-chip, inductor-to-inductor and substrate-to-inductor coupling were investigated.

Original languageEnglish
Pages199-200
Number of pages2
StatePublished - 2001
Event2001 VLSI Circuits Symposium - Kyoto, Japan
Duration: 14 Jun 200116 Jun 2001

Conference

Conference2001 VLSI Circuits Symposium
CountryJapan
CityKyoto
Period14/06/0116/06/01

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