This paper presents a complete portfolio of silicon integrated inductors in a 0.18μm CMOS technology. In addition to inductor design, we also present a complete optimization methodology with associated modeling and key characterization. Our inductor quality factors have been enhanced by optimizing patterned ground shield and taper coils, or use Copper metallization. Quality-factor peak can further be optimized at application-specific frequency band with our optimization algorithm. To facilitate IC design with inductors, a novel model considering eddy current loss was developed. Finally, to integrate inductors into a system-chip, inductor-to-inductor and substrate-to-inductor coupling were investigated.
|Number of pages||2|
|State||Published - 2001|
|Event||2001 VLSI Circuits Symposium - Kyoto, Japan|
Duration: 14 Jun 2001 → 16 Jun 2001
|Conference||2001 VLSI Circuits Symposium|
|Period||14/06/01 → 16/06/01|