Silicon integrated high performance inductors in a 0.18μm CMOS technology for MMIC

H. M. Hsu; J. G. Su; S. C. Wong; Y. C. Sun; C. Y. Chang; T. Y. Huang; C. C. Tsai; C. H. Lin; R. S. Liou; R. Y. Chang; T. H. Yeh; C. H. Chen; C. F. Huang; H. D. Huang; C. W. Chen

Silicon integrated high performance inductors in a 0.18μm CMOS technology for MMIC

H. M. Hsu^*, J. G. Su, S. C. Wong, Y. C. Sun, C. Y. Chang, T. Y. Huang, C. C. Tsai, C. H. Lin, R. S. Liou, R. Y. Chang, T. H. Yeh, C. H. Chen, C. F. Huang, H. D. Huang, C. W. Chen

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Contribution to conference › Paper › peer-review

15 Scopus citations

Abstract

This paper presents a complete portfolio of silicon integrated inductors in a 0.18μm CMOS technology. In addition to inductor design, we also present a complete optimization methodology with associated modeling and key characterization. Our inductor quality factors have been enhanced by optimizing patterned ground shield and taper coils, or use Copper metallization. Quality-factor peak can further be optimized at application-specific frequency band with our optimization algorithm. To facilitate IC design with inductors, a novel model considering eddy current loss was developed. Finally, to integrate inductors into a system-chip, inductor-to-inductor and substrate-to-inductor coupling were investigated.

Original language	English
Pages	199-200
Number of pages	2
State	Published - 2001
Event	2001 VLSI Circuits Symposium - Kyoto, Japan Duration: 14 Jun 2001 → 16 Jun 2001

Conference

Conference	2001 VLSI Circuits Symposium
Country	Japan
City	Kyoto
Period	14/06/01 → 16/06/01

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title = "Silicon integrated high performance inductors in a 0.18μm CMOS technology for MMIC",

abstract = "This paper presents a complete portfolio of silicon integrated inductors in a 0.18μm CMOS technology. In addition to inductor design, we also present a complete optimization methodology with associated modeling and key characterization. Our inductor quality factors have been enhanced by optimizing patterned ground shield and taper coils, or use Copper metallization. Quality-factor peak can further be optimized at application-specific frequency band with our optimization algorithm. To facilitate IC design with inductors, a novel model considering eddy current loss was developed. Finally, to integrate inductors into a system-chip, inductor-to-inductor and substrate-to-inductor coupling were investigated.",

author = "Hsu, {H. M.} and Su, {J. G.} and Wong, {S. C.} and Sun, {Y. C.} and Chang, {C. Y.} and Huang, {T. Y.} and Tsai, {C. C.} and Lin, {C. H.} and Liou, {R. S.} and Chang, {R. Y.} and Yeh, {T. H.} and Chen, {C. H.} and Huang, {C. F.} and Huang, {H. D.} and Chen, {C. W.}",

year = "2001",

language = "English",

pages = "199--200",

note = "null ; Conference date: 14-06-2001 Through 16-06-2001",

}

Silicon integrated high performance inductors in a 0.18μm CMOS technology for MMIC. / Hsu, H. M.; Su, J. G.; Wong, S. C.; Sun, Y. C.; Chang, C. Y.; Huang, T. Y.; Tsai, C. C.; Lin, C. H.; Liou, R. S.; Chang, R. Y.; Yeh, T. H.; Chen, C. H.; Huang, C. F.; Huang, H. D.; Chen, C. W.

2001. 199-200 Paper presented at 2001 VLSI Circuits Symposium, Kyoto, Japan.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - Silicon integrated high performance inductors in a 0.18μm CMOS technology for MMIC

AU - Hsu, H. M.

AU - Su, J. G.

AU - Wong, S. C.

AU - Sun, Y. C.

AU - Chang, C. Y.

AU - Huang, T. Y.

AU - Tsai, C. C.

AU - Lin, C. H.

AU - Liou, R. S.

AU - Chang, R. Y.

AU - Yeh, T. H.

AU - Chen, C. H.

AU - Huang, C. F.

AU - Huang, H. D.

AU - Chen, C. W.

PY - 2001

Y1 - 2001

N2 - This paper presents a complete portfolio of silicon integrated inductors in a 0.18μm CMOS technology. In addition to inductor design, we also present a complete optimization methodology with associated modeling and key characterization. Our inductor quality factors have been enhanced by optimizing patterned ground shield and taper coils, or use Copper metallization. Quality-factor peak can further be optimized at application-specific frequency band with our optimization algorithm. To facilitate IC design with inductors, a novel model considering eddy current loss was developed. Finally, to integrate inductors into a system-chip, inductor-to-inductor and substrate-to-inductor coupling were investigated.

AB - This paper presents a complete portfolio of silicon integrated inductors in a 0.18μm CMOS technology. In addition to inductor design, we also present a complete optimization methodology with associated modeling and key characterization. Our inductor quality factors have been enhanced by optimizing patterned ground shield and taper coils, or use Copper metallization. Quality-factor peak can further be optimized at application-specific frequency band with our optimization algorithm. To facilitate IC design with inductors, a novel model considering eddy current loss was developed. Finally, to integrate inductors into a system-chip, inductor-to-inductor and substrate-to-inductor coupling were investigated.

UR - http://www.scopus.com/inward/record.url?scp=0034795416&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0034795416

SP - 199

EP - 200

Y2 - 14 June 2001 through 16 June 2001

ER -

Silicon integrated high performance inductors in a 0.18μm CMOS technology for MMIC

Abstract

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