Silicon-germanium structure in surrounding-gate strained silicon nanowire field effect transistors

Yi-Ming Li*, Jam Wem Lee, Hung Mu Chou

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

8 Scopus citations

Abstract

In this paper we numerically examine the electrical characteristics of surrounding-gate strained silicon nanowire field effect transistors (FETs) by changing the radius (RSiGe) of silicon-germanium (SiGe) wire. Due to the higher electron mobility, the n-type FETs with strained silicon channel films do enhance driving capability (∼8% increment on the drain current) in comparison with the pure Si one. The leakage current and transfer characteristics, the threshold-voltage (Vt), the drain induced barrier height lowering (DIBL), and the gate capacitance (CG) are estimated with respect to different gate length (LG), gate bias (VG), and RSiGe. For short channel effects, such as Vt roll-off and DIBL, the surrounding-gate strained silicon nanowire FET sustains similar characteristics with the pure Si one.

Original languageEnglish
Pages (from-to)251-255
Number of pages5
JournalJournal of Computational Electronics
Volume3
Issue number3-4
DOIs
StatePublished - Oct 2004

Keywords

  • Drain induced barrier height lowering
  • Gate capacitance
  • Nanowire FET
  • Simulation
  • Strained silicon
  • Surrounding-gate
  • Threshold-voltage roll-off

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