Silicide Optimization for Electrostatic Discharge Protection Devices in Sub- 100 nm CMOS Circuit Design

Jam Wem Lee*, Yi-Ming Li, Howard Tang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

In this paper we propose a novel suicide optimization method for electrostatic discharge protection in nanoscale MOSFET devices. Based on the developed techniques, it has found that a comprehensive suicide optimization could be easily achieved on gate, drain, and source sides only with few designed testkeys. Compared with the fabricated and measured results, this technique also demonstrates very high characterization efficiency for various conditions. The method is in particular useful in deep sub-01 μm CMOS very large scale integrated circuit design, in which requires a robust electrostatic discharge protection device. Besides, a circuit level design of electrostatic discharge protection is also discussed for the system performance and speed evaluation.

Original languageEnglish
Title of host publicationProceedings of the International Conference on VLSI, VLSI 03
EditorsH.R. Arbania, L.T. Yang
Pages251-257
Number of pages7
StatePublished - Jan 2003
EventProceedings of the International Conference on VLSI, VLSI'03 - Las Vegas, NV, United States
Duration: 23 Jun 200326 Jun 2003

Publication series

NameProceedings of the International Conference on VLSI

Conference

ConferenceProceedings of the International Conference on VLSI, VLSI'03
CountryUnited States
CityLas Vegas, NV
Period23/06/0326/06/03

Keywords

  • 2D simulation and optimization
  • ESD
  • Nanodevice
  • Silicide
  • VLSI circuit

Fingerprint Dive into the research topics of 'Silicide Optimization for Electrostatic Discharge Protection Devices in Sub- 100 nm CMOS Circuit Design'. Together they form a unique fingerprint.

  • Cite this

    Lee, J. W., Li, Y-M., & Tang, H. (2003). Silicide Optimization for Electrostatic Discharge Protection Devices in Sub- 100 nm CMOS Circuit Design. In H. R. Arbania, & L. T. Yang (Eds.), Proceedings of the International Conference on VLSI, VLSI 03 (pp. 251-257). (Proceedings of the International Conference on VLSI).