Silicide Optimization for Electrostatic Discharge Protection Devices in Sub- 100 nm CMOS Circuit Design

Jam Wem Lee; Yi-Ming Li; Howard Tang

Silicide Optimization for Electrostatic Discharge Protection Devices in Sub- 100 nm CMOS Circuit Design

Jam Wem Lee^*, Yi-Ming Li, Howard Tang

^*Corresponding author for this work

Institute of Communications Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

In this paper we propose a novel suicide optimization method for electrostatic discharge protection in nanoscale MOSFET devices. Based on the developed techniques, it has found that a comprehensive suicide optimization could be easily achieved on gate, drain, and source sides only with few designed testkeys. Compared with the fabricated and measured results, this technique also demonstrates very high characterization efficiency for various conditions. The method is in particular useful in deep sub-01 μm CMOS very large scale integrated circuit design, in which requires a robust electrostatic discharge protection device. Besides, a circuit level design of electrostatic discharge protection is also discussed for the system performance and speed evaluation.

Original language	English
Title of host publication	Proceedings of the International Conference on VLSI, VLSI 03
Editors	H.R. Arbania, L.T. Yang
Pages	251-257
Number of pages	7
State	Published - Jan 2003
Event	Proceedings of the International Conference on VLSI, VLSI'03 - Las Vegas, NV, United States Duration: 23 Jun 2003 → 26 Jun 2003

Publication series

Name	Proceedings of the International Conference on VLSI

Conference

Conference	Proceedings of the International Conference on VLSI, VLSI'03
Country	United States
City	Las Vegas, NV
Period	23/06/03 → 26/06/03

Keywords

2D simulation and optimization
ESD
Nanodevice
Silicide
VLSI circuit

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Link to publication in Scopus

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Lee, J. W., Li, Y-M., & Tang, H. (2003). Silicide Optimization for Electrostatic Discharge Protection Devices in Sub- 100 nm CMOS Circuit Design. In H. R. Arbania, & L. T. Yang (Eds.), Proceedings of the International Conference on VLSI, VLSI 03 (pp. 251-257). (Proceedings of the International Conference on VLSI).

@inproceedings{5fd0a3ad9a3d4c00bfbc588cee19e9bc,

title = "Silicide Optimization for Electrostatic Discharge Protection Devices in Sub- 100 nm CMOS Circuit Design",

abstract = "In this paper we propose a novel suicide optimization method for electrostatic discharge protection in nanoscale MOSFET devices. Based on the developed techniques, it has found that a comprehensive suicide optimization could be easily achieved on gate, drain, and source sides only with few designed testkeys. Compared with the fabricated and measured results, this technique also demonstrates very high characterization efficiency for various conditions. The method is in particular useful in deep sub-01 μm CMOS very large scale integrated circuit design, in which requires a robust electrostatic discharge protection device. Besides, a circuit level design of electrostatic discharge protection is also discussed for the system performance and speed evaluation.",

keywords = "2D simulation and optimization, ESD, Nanodevice, Silicide, VLSI circuit",

author = "Lee, {Jam Wem} and Yi-Ming Li and Howard Tang",

year = "2003",

month = jan,

language = "English",

isbn = "1932415106",

series = "Proceedings of the International Conference on VLSI",

pages = "251--257",

editor = "H.R. Arbania and L.T. Yang",

booktitle = "Proceedings of the International Conference on VLSI, VLSI 03",

note = "null ; Conference date: 23-06-2003 Through 26-06-2003",

}

Lee, JW, Li, Y-M & Tang, H 2003, Silicide Optimization for Electrostatic Discharge Protection Devices in Sub- 100 nm CMOS Circuit Design. in HR Arbania & LT Yang (eds), Proceedings of the International Conference on VLSI, VLSI 03. Proceedings of the International Conference on VLSI, pp. 251-257, Proceedings of the International Conference on VLSI, VLSI'03, Las Vegas, NV, United States, 23/06/03.

Silicide Optimization for Electrostatic Discharge Protection Devices in Sub- 100 nm CMOS Circuit Design. / Lee, Jam Wem; Li, Yi-Ming; Tang, Howard.

Proceedings of the International Conference on VLSI, VLSI 03. ed. / H.R. Arbania; L.T. Yang. 2003. p. 251-257 (Proceedings of the International Conference on VLSI).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Silicide Optimization for Electrostatic Discharge Protection Devices in Sub- 100 nm CMOS Circuit Design

AU - Lee, Jam Wem

AU - Li, Yi-Ming

AU - Tang, Howard

PY - 2003/1

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N2 - In this paper we propose a novel suicide optimization method for electrostatic discharge protection in nanoscale MOSFET devices. Based on the developed techniques, it has found that a comprehensive suicide optimization could be easily achieved on gate, drain, and source sides only with few designed testkeys. Compared with the fabricated and measured results, this technique also demonstrates very high characterization efficiency for various conditions. The method is in particular useful in deep sub-01 μm CMOS very large scale integrated circuit design, in which requires a robust electrostatic discharge protection device. Besides, a circuit level design of electrostatic discharge protection is also discussed for the system performance and speed evaluation.

AB - In this paper we propose a novel suicide optimization method for electrostatic discharge protection in nanoscale MOSFET devices. Based on the developed techniques, it has found that a comprehensive suicide optimization could be easily achieved on gate, drain, and source sides only with few designed testkeys. Compared with the fabricated and measured results, this technique also demonstrates very high characterization efficiency for various conditions. The method is in particular useful in deep sub-01 μm CMOS very large scale integrated circuit design, in which requires a robust electrostatic discharge protection device. Besides, a circuit level design of electrostatic discharge protection is also discussed for the system performance and speed evaluation.

KW - 2D simulation and optimization

KW - ESD

KW - Nanodevice

KW - Silicide

KW - VLSI circuit

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M3 - Conference contribution

AN - SCOPUS:1642355946

SN - 1932415106

T3 - Proceedings of the International Conference on VLSI

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BT - Proceedings of the International Conference on VLSI, VLSI 03

A2 - Arbania, H.R.

A2 - Yang, L.T.

Y2 - 23 June 2003 through 26 June 2003

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