Si nanowire technology

Hiroshi Iwai*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Recently, CMOS downsizing has been accelerated very aggressively in both production and research levels. However, it is still questionable if we can successfully introduce deep sub-10 nm CMOS LSIs into market, due to performance concerns - such as Ion/Ioff ratio, current drive, variation in the electrical characteristics, concerns for the yield, reliability and manufacturing cost. We have conducted nano-CMOS studies in advance to provide possible solutions to the future expected problems. Si Nanowire FETs have been found to have very promising characteristics with high Ion/Ioff ratio and high drive current which could give them a strong foothold in the near future device structures.

Original languageEnglish
Title of host publicationDielectric Materials and Metals for Nanoelectronics and Photonics 10
Pages251-260
Number of pages10
Edition4
DOIs
StatePublished - 2012
EventSymposium on Dielectric Materials and Metals for Nanoelectronics and Photonics - 10 - 222nd ECS Meeting - Honolulu, HI, United States
Duration: 7 Oct 201212 Oct 2012

Publication series

NameECS Transactions
Number4
Volume50
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Conference

ConferenceSymposium on Dielectric Materials and Metals for Nanoelectronics and Photonics - 10 - 222nd ECS Meeting
CountryUnited States
CityHonolulu, HI
Period7/10/1212/10/12

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  • Cite this

    Iwai, H. (2012). Si nanowire technology. In Dielectric Materials and Metals for Nanoelectronics and Photonics 10 (4 ed., pp. 251-260). (ECS Transactions; Vol. 50, No. 4). https://doi.org/10.1149/05004.0251ecst