Si-MOSFET scaling down to deep-sub-0.1-micron range and future of silicon LSI

Hiroshi Iwai*, Hisayo Sasaki Momose, Yasuhiro Katsumata

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

8 Scopus citations

Abstract

The tremendous progress made with silicon LSIs over the past 25 years has been driven by the miniaturization of MOSFETs. Down-sizing MOSFETs below the 0.1 micron range, however, is proving technologically very difficult due to certain physical limitations. In this paper, we will demonstrate certain ways in which MOSFETs can be taken down to the deep-sub-0.1 micron regime, and also give our views on future LSIs using these MOSFETs.

Original languageEnglish
Pages262-267
Number of pages6
StatePublished - 1995
EventProceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan
Duration: 31 May 19952 Jun 1995

Conference

ConferenceProceedings of the 1995 International Symposium on VLSI Technology, Systems, and Applications
CityTaipei, Taiwan
Period31/05/952/06/95

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