SERL: Soft error resilient latch design

Chun Wei Jacky Chang; Hsuan Ming Ryan Huang; Yuwen Lin; Charles H.P. Wen

doi:10.1109/VLSI-DAT.2016.7482555

SERL: Soft error resilient latch design

Chun Wei Jacky Chang, Hsuan Ming Ryan Huang, Yuwen Lin, Charles H.P. Wen

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

Soft errors, radiation-induced transient faults latched by memory elements, have emerged to be one dominant failure mechanism for scaled CMOS designs. Therefore, this paper presents a robust design named soft error resilient latch (SERL). Compared to BISER, one of the latest latch designs, SERL demonstrates better soft error protection with smaller area overhead.

Original language	English
Title of host publication	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467394987
DOIs	https://doi.org/10.1109/VLSI-DAT.2016.7482555
State	Published - 31 May 2016
Event	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan Duration: 25 Apr 2016 → 27 Apr 2016

Publication series

Name	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Conference

Conference	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Country	Taiwan
City	Hsinchu
Period	25/04/16 → 27/04/16

Keywords

BISER
SER
SET
SEU

Access to Document

10.1109/VLSI-DAT.2016.7482555

Link to publication in Scopus

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Cite this

Chang, C. W. J., Huang, H. M. R., Lin, Y., & Wen, C. H. P. (2016). SERL: Soft error resilient latch design. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 [7482555] (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2016.7482555

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title = "SERL: Soft error resilient latch design",

abstract = "Soft errors, radiation-induced transient faults latched by memory elements, have emerged to be one dominant failure mechanism for scaled CMOS designs. Therefore, this paper presents a robust design named soft error resilient latch (SERL). Compared to BISER, one of the latest latch designs, SERL demonstrates better soft error protection with smaller area overhead.",

keywords = "BISER, SER, SET, SEU",

author = "Chang, {Chun Wei Jacky} and Huang, {Hsuan Ming Ryan} and Yuwen Lin and Wen, {Charles H.P.}",

year = "2016",

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doi = "10.1109/VLSI-DAT.2016.7482555",

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booktitle = "2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016",

note = "null ; Conference date: 25-04-2016 Through 27-04-2016",

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Chang, CWJ, Huang, HMR, Lin, Y & Wen, CHP 2016, SERL: Soft error resilient latch design. in 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016., 7482555, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Institute of Electrical and Electronics Engineers Inc., 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Hsinchu, Taiwan, 25/04/16. https://doi.org/10.1109/VLSI-DAT.2016.7482555

SERL : Soft error resilient latch design. / Chang, Chun Wei Jacky; Huang, Hsuan Ming Ryan; Lin, Yuwen; Wen, Charles H.P.

2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7482555 (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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