SERL: Soft error resilient latch design

Chun Wei Jacky Chang, Hsuan Ming Ryan Huang, Yuwen Lin, Charles H.P. Wen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Soft errors, radiation-induced transient faults latched by memory elements, have emerged to be one dominant failure mechanism for scaled CMOS designs. Therefore, this paper presents a robust design named soft error resilient latch (SERL). Compared to BISER, one of the latest latch designs, SERL demonstrates better soft error protection with smaller area overhead.

Original languageEnglish
Title of host publication2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467394987
DOIs
StatePublished - 31 May 2016
Event2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan
Duration: 25 Apr 201627 Apr 2016

Publication series

Name2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Conference

Conference2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
CountryTaiwan
CityHsinchu
Period25/04/1627/04/16

Keywords

  • BISER
  • SER
  • SET
  • SEU

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    Chang, C. W. J., Huang, H. M. R., Lin, Y., & Wen, C. H. P. (2016). SERL: Soft error resilient latch design. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 [7482555] (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2016.7482555