Abstract
Soft errors, radiation-induced transient faults latched by memory elements, have emerged to be one dominant failure mechanism for scaled CMOS designs. Therefore, this paper presents a robust design named soft error resilient latch (SERL). Compared to BISER, one of the latest latch designs, SERL demonstrates better soft error protection with smaller area overhead.
Original language | English |
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Title of host publication | 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781467394987 |
DOIs | |
State | Published - 31 May 2016 |
Event | 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan Duration: 25 Apr 2016 → 27 Apr 2016 |
Publication series
Name | 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 |
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Conference
Conference | 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 |
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Country | Taiwan |
City | Hsinchu |
Period | 25/04/16 → 27/04/16 |
Keywords
- BISER
- SER
- SET
- SEU