Separate clock network voltage for correcting random errors in ULV clocked storage cells

Shien Chun Luo, Kuo Chiang Chang, Ming Pin Chen, Ching Ji Huang, Yi Fang Chiu, Po Hsun Chen, Liang Chia Cheng, Chih-Wei Liu, Yuan Hua Chu

Research output: Contribution to journalArticlepeer-review


This brief presents an implementation of ultralow-power microcontrollers that use a separate clock network voltage (SCNV) to correct unexpected errors produced by on-chip variations (OCVs). Separating the clock network voltage requires amendments in the standard cell library and physical designs. Here, the experiments used a 65-nm technology that exhibited considerable OCVs, which caused write and retention errors in clocked storage cells and limited the voltage scaling of microcontrollers. Using the SCNV provides an extraordinary operability to correct errors in the low-voltage clocked storage cells. In addition, the area overhead of the proposed implementation is negligible. Applying the SCNV, the measurement results indicate that the microcontrollers can be operated below 0.3 V, over 0.15-V extension in voltage scaling, and achieve the optimal energy consumption at 0.34 V. Separating the clock network voltage has tradeoff issues in system timing and energy consumption based on the measurement results, and this brief discusses proper applications.

Original languageEnglish
Article number6895148
Pages (from-to)947-951
Number of pages5
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number12
StatePublished - 1 Dec 2014


  • Digital clocking
  • dynamic voltage scaling (DVS)
  • flip-flop
  • process variation
  • subthreshold circuit.

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