Semi-systolic array based motion estimation processor design

Mei Cheng Lu*, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalConference article

4 Scopus citations

Abstract

This paper presents a new VLSI architecture for full-search block matching algorithm. The proposed architecture has two specific features: (1) it has a processor element (PE) array which provides sufficient computational power, where PE's work in a semi-systolic style and (2) it contains stream memory banks which provide scheduled data flow to reduce idle operations within PE array. By exploiting broadcasting and local data communications, hardware efficiency of the proposed architecture can be up to 100%, which outperforms those systolic-array solutions found in the literature.

Original languageEnglish
Pages (from-to)3299-3302
Number of pages4
JournalICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Volume5
DOIs
StatePublished - 1 Jan 1995
EventProceedings of the 1995 20th International Conference on Acoustics, Speech, and Signal Processing. Part 2 (of 5) - Detroit, MI, USA
Duration: 9 May 199512 May 1995

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