Self-aligned shallow trench isolation recess effect on cell performance and reliability of 42nm NAND flash memory

C. H. Liu, Y. M. Lin, Riichiro Shirota, H. C. Wei, L. T. Kuo, C. Han Liu, S. H. Chen, H. P. Hwang, Y. Sakamoto, S. Pittikoun

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Self-aligned shallow trench isolation recess effect on 42nm node NAND flash to achieve high performance and good reliability has been studied and demonstrated. As cell STI recess is increased by 23nm, 29% narrower cell Vth distribution width and 54% less cell Vth shift after 125°C, 2 hours can be obtained. Furthermore, the endurance window is obviously improved ∼0.5V as the distance of the active area edge to control gate (CG) is increased at the same time. Deeper STI recess and enough active area edge to CG distance are a promising profile for floating gate based NAND flash at 42nm node and beyond.

Original languageEnglish
Title of host publicationProceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
Pages46-47
Number of pages2
DOIs
StatePublished - 20 Oct 2010
Event2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010 - Hsin Chu, Taiwan
Duration: 26 Apr 201028 Apr 2010

Publication series

NameProceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010

Conference

Conference2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
CountryTaiwan
CityHsin Chu
Period26/04/1028/04/10

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  • Cite this

    Liu, C. H., Lin, Y. M., Shirota, R., Wei, H. C., Kuo, L. T., Liu, C. H., Chen, S. H., Hwang, H. P., Sakamoto, Y., & Pittikoun, S. (2010). Self-aligned shallow trench isolation recess effect on cell performance and reliability of 42nm NAND flash memory. In Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010 (pp. 46-47). [5488956] (Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010). https://doi.org/10.1109/VTSA.2010.5488956