Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap

Lan Wei, Deng Jie, Li-Wen Chang, Keunwoo Kim, Ching-Te Chuang, H.-S.Philip Wong

Research output: Contribution to journalArticle

26 Scopus citations

Abstract

We propose a path for extending the technology roadmap when currently considered technology boosters (e.g., strain, high-kappa/metal gate) reach their limits and physical gate length can no longer be effectively scaled down. By judiciously engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, we propose scenarios of selective device structure scaling that will enable technology scaling and contacted gate pitch scaling for several generations beyond the currently perceived limits.
Original languageEnglish
Pages (from-to)312-320
Number of pages9
JournalIEEE Transactions on Electron Devices
Volume56
Issue number2
DOIs
StatePublished - Feb 2009

Keywords

  • CMOS; contacted gate pitch; device geometry; device scaling; footprint; parasitic
  • IMPACT; MOSFET

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