We propose a path for extending the technology roadmap when currently considered technology boosters (e.g., strain, high-kappa/metal gate) reach their limits and physical gate length can no longer be effectively scaled down. By judiciously engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, we propose scenarios of selective device structure scaling that will enable technology scaling and contacted gate pitch scaling for several generations beyond the currently perceived limits.
- CMOS; contacted gate pitch; device geometry; device scaling; footprint; parasitic
- IMPACT; MOSFET
Wei, L., Jie, D., Chang, L-W., Kim, K., Chuang, C-T., & Wong, H-S. P. (2009). Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap. IEEE Transactions on Electron Devices, 56(2), 312-320. https://doi.org/10.1109/TED.2008.2010573