Segmented bus design for low-power systems

J. Y. Chen*, W. B. Jone, J. S. Wang, H. I. Lu, Tien-Fu Chen

*Corresponding author for this work

Research output: Contribution to journalArticle

61 Scopus citations

Abstract

This paper1 proposes a bus-segmentation method that efficiently reduces the switched capacitance on the bus. The power consumed by the bus can, therefore, be substantially reduced. The basic idea of bus segmentation is to partition the bus into several bus segments separated by pass transistors. Highly communicating devices are located to adjacent bus segments, thus, most data communication can be achieved by switching a small portion of the bus segments. As a result, power consumption and critical path delay are both reduced. Experimental results obtained by simulating a delay model and a power model demonstrate that the proposed segmented bus system reduces bus power by about 60%-70% and improves critical bus delay by about 10%-30%.

Original languageEnglish
Pages (from-to)25-29
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume7
Issue number1
DOIs
StatePublished - 1 Dec 1999

Keywords

  • Bus communication
  • Bus graph
  • Bus segmentation
  • Bus tree
  • Low-power systems

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