Sealing bump with bottom-up Cu TSV plating fabrication in 3-D integration scheme

Cheng Hao Chiang, Li Min Kuo, Yu Chen Hu, Wen Chun Huang, Cheng Ta Ko, Kuan-Neng Chen

Research output: Contribution to journalArticlepeer-review

15 Scopus citations

Abstract

A sealing bump approach for the simplification of the conventional bottom-up copper through-silicon via (TSV) plating process flow is developed to reduce the process steps and increase the throughput without sacrificing the structure integrity and electrical performance. In this approach, TSV and bump formation can be achieved simultaneously through the bottom-up plating. Results from the analysis reveal excellent electrical characteristics and quality examination, which indicate that the proposed approach may be a good candidate for the TSV fabrication in 3-D integration.

Original languageEnglish
Article number6482589
Pages (from-to)671-673
Number of pages3
JournalIEEE Electron Device Letters
Volume34
Issue number5
DOIs
StatePublished - 26 Mar 2013

Keywords

  • 3-D integration
  • bottom-up plating
  • through-silicon via (TSV)

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