Schottky s/d MOSFETs with high-Kgate dielectrics and metal gate electrodes

Shiyang Zhu*, Jingde Chen, H. Y. Yu, S. J. Whang, J. H. Chen, C. Shen, M. F. Li, S. J. Lee, Chunxiang Zhu, D. S.H. Chan, Anyan Du, C. H. Tung, Jagar Singh, Albert Chin, D. L. Kwong

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

Bulk Schottky suicide source/drain n- and p-MOS transistors (SSDTs) with EOT=2.0-2.5nm HfO 2 gate dielectric and HfN/TaN metal gate have been successfully demonstrated using a low temperature process. P-SSDTs with PtSi suicide show excellent electrical performance of I on ∼10 7-10 8 and subthreshold slop of 66 mV/dec. N-SSDTs with YbSi 2-x silicide have also demonstrated a very promising characteristic with a recorded high I on/I off radio of∼ 10 7 and subthreshold slope of 75mV/dec. To the best of our knowledge, these are the best SSDTs data reported so far. The implant free low temperature process relaxes the thermal budget of high-K dielectric and metal gate materials. Our results are expected to be further improved when using ultra-thin-body (UTB) SOI structures, -showing great potential of this low temperature process SSDTs for future sub-tenth micron CMOS technology.

Original languageEnglish
Pages53-56
Number of pages4
StatePublished - 1 Dec 2004
Event2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004 - Beijing, China
Duration: 18 Oct 200421 Oct 2004

Conference

Conference2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004
CountryChina
CityBeijing
Period18/10/0421/10/04

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