Scheduling of multiple in-line steppers for semiconductor wafer fabs

Chie Wun Chiou, Muh-Cherng Wu*

*Corresponding author for this work

Research output: Contribution to journalArticle

5 Scopus citations

Abstract

A few prior studies noticed that an in-line stepper (a bottleneck machine in a semiconductor fab) may have a capacity loss while operated in a low-yield scenario. To alleviate such a capacity loss, some meta-heuristic algorithms for scheduling a single in-line stepper were proposed. Yet, in practice, there are multiple in-line steppers to be scheduled in a fab. This article aims to enhance prior algorithms so as to deal with the scheduling for multiple in-line steppers. Compared to prior studies, this research has to additionally consider how to appropriately allocate jobs to various machines. We enhance prior algorithms by developing a chromosome-decoding scheme which can yield a job-allocation decision for any given chromosome (or job sequence). Seven enhanced versions of meta-heuristic algorithms (genetic algorithm, Tabu, GA-Tabu, simulated annealing, M-MMAX, PACO and particle swarm optimisation) were then proposed and tested. Numerical experiments indicate that the GA-Tabu method outperforms the others. In addition, the lower the process yield, the better is the performance of the GA-Tabu algorithm.

Original languageEnglish
Pages (from-to)384-398
Number of pages15
JournalInternational Journal of Systems Science
Volume45
Issue number3
DOIs
StatePublished - 1 Mar 2014

Keywords

  • flow shop
  • genetic algorithm
  • meta-heuristic algorithms
  • port capacity constraints
  • scheduling
  • semiconductor

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