Scannable pulse-to-static conversion register array for self-timed circuits

Wei Hwang, Rajiv V. Joshi, George D. Gristede

Research output: Contribution to journalArticle

Abstract

This paper describes the design and hardware results of a scannable pulse-to-static conversion register array for self-timed circuits. The circuits include a self-timed control circuit and a 64-bit register array, both designed utilizing self-resetting CMOS (SRCMOS) circuit techniques. The self-timed feature of the control block allows it to require only one system clock input. The evaluation, reset, and write-enable controls are all generated within the control macro. The register array is a level-sensitive scan design, which is compatible and complies with SRCMOS test modes. This type of register array can facilitate the synchronous/asynchronous interfaces, pipelined operation, power management, and testing of advanced digital systems employing a mixture of static and dynamic circuits to achieve low power and high performance.

Original languageEnglish
Pages (from-to)125-128
Number of pages4
JournalIEEE Journal of Solid-State Circuits
Volume35
Issue number1
DOIs
StatePublished - 1 Jan 2000

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