Scan-chain reordering for minimizing scan-shift power based on non-specified test cubes

Yu Ze Wu*, Chia-Tso Chao

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

18 Scopus citations

Abstract

This paper proposes a scan-cell reordering scheme, named ROBPR, to reduce the signal transitions during test mode while preserving the don 't-care bits in the test patterns for a later optimization. Combined with a pattern-filling technique, the proposed scheme utilizes both response correlation and pattern correlation to simultaneously minimize scan-out and scan-in transitions. A series of experiments demonstrate the effectiveness and superiority of the proposed scheme on reducing total scan-shift transitions. The trade-off between our power-driven scan-cell reordering and a routing-driven scan-cell reordering is discussed based on experiments as well.

Original languageEnglish
Title of host publicationProceedings - 26th IEEE VLSI Test Symposium, VTS08
Pages147-154
Number of pages8
DOIs
StatePublished - 2 Oct 2008
Event26th IEEE VLSI Test Symposium, VTS08 - San Diego, CA, United States
Duration: 27 Apr 20081 May 2008

Publication series

NameProceedings of the IEEE VLSI Test Symposium

Conference

Conference26th IEEE VLSI Test Symposium, VTS08
CountryUnited States
CitySan Diego, CA
Period27/04/081/05/08

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