Scaling of gate dielectric on Ge substrate

Yung Hsiang Chan, Bing-Yue Tsui

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Scaling of Hf-based and Zr-based gate dielectric stack on Ge is investigated. Effects of dielectric thickness and thermal budget on the MOS device characteristics are studied. Tradeoff among effective oxide thickness (EOT), leakage current density (JG), interface state density (Dit), and hysteresis are observed and discussed. With the same HfO2 and ZrO2 thickness, the ZrO2 samples exhibit lower Dit and smaller hysteresis but slightly higher JG. The crystallized ZrO2 exhibits the best JG-EOT performance. However, as the EOT becomes thinner than 0.8 nm, it is hard to lower Dit to 1×1012 eV-1cm-2. According to these results, novel techniques for Ge surface passivation and ZrO2 crystallization are required.

Original languageEnglish
Title of host publication2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509058051
DOIs
StatePublished - 7 Jun 2017
Event2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 - Hsinchu, Taiwan
Duration: 24 Apr 201727 Apr 2017

Publication series

Name2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017

Conference

Conference2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
CountryTaiwan
CityHsinchu
Period24/04/1727/04/17

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