Scaling of EOT beyond 0.5nm

P. Ahmet*, D. Kitayama, T. Kaneda, T. Suzuki, T. Koyanagi, M. Kouda, M. Mamatrishat, T. Kawanago, K. Kakushima, H. Iwai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we report our approaches in realizing EOT of 0.5nm and below with rare earth La2O3 high-k gate dielectric. An EOT of 0.43 nm was obtained from a TiN/W/La2O3(3nm)/n-Si capacitor by optimizing the thickness W layer. Our results show that a proper gate electrode is one of the most important factors for realizing EOT below 0.5nm.

Original languageEnglish
Title of host publicationICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
Pages994-996
Number of pages3
DOIs
StatePublished - 2010
Event2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China
Duration: 1 Nov 20104 Nov 2010

Publication series

NameICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Conference

Conference2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
CountryChina
CityShanghai
Period1/11/104/11/10

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    Ahmet, P., Kitayama, D., Kaneda, T., Suzuki, T., Koyanagi, T., Kouda, M., Mamatrishat, M., Kawanago, T., Kakushima, K., & Iwai, H. (2010). Scaling of EOT beyond 0.5nm. In ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings (pp. 994-996). [5667512] (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings). https://doi.org/10.1109/ICSICT.2010.5667512