Scaling of CMOS FinFETs towards 10 nm

Hao Yu Chen, Chien Chao Huang, Cheng Chuan Huang, Chang Yun Chang, Yee Chia Yeo, Fu Liang Yang, Chen-Ming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

CMOS FinFETs with 35 nm gate length Lg and performance parameters exceeding that of ITRS projections are fabricated. Device simulations are performed to match the experimental results and to explore the scalability and optimization of FinFETs to 10 nm gate length. Symmetrical NMOS and PMOS V/s, low off-state leakages, and high drive currents can be realized using dual-doped poly-Si or mid-gap gate electrodes.

Original languageEnglish
Title of host publicationVLSI 2003 - 2003 20th International Symposium on VLSI Technology, Systems and Applications, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages46-48
Number of pages3
ISBN (Electronic)0780377656
DOIs
StatePublished - 1 Jan 2003
Event20th International Symposium on VLSI Technology, Systems and Applications, VLSI 2003 - Hsinchu, Taiwan
Duration: 6 Oct 20038 Oct 2003

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
Volume2003-January
ISSN (Print)1930-8868

Conference

Conference20th International Symposium on VLSI Technology, Systems and Applications, VLSI 2003
CountryTaiwan
CityHsinchu
Period6/10/038/10/03

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